1. Field of the Invention
The present invention relates to a circuit for generating a boosted signal for a word line and, more particularly, to a circuit for generating a boosted signal for a word line used as a peripheral circuit of a dynamic random access memory (RAM).
2. Description of the Prior Art
FIG. 1 is a block diagram showing a portion of a peripheral circuit of a conventional dynamic RAM, i.e. a peripheral circuit portion for operating a circuit for generating a boosted signal for a word line, including a circuit for generating a control signal for controlling the peripheral circuit portion.
The peripheral circuit shown in FIG. 1 comprises: a central processing unit (CPU) 58; a precharge start signal generating circuit 51 for generating a precharge start signal .phi.R in synchronization with an external RAS signal outputted from the CPU 58; a boosting trigger signal generating circuit 52 for generating a boosting trigger signal .phi.T to urge a start of boosting after a certain delay upon receipt of the precharge start signal .phi.R; a boosted signal generating circuit 55 for providing a word line driving signal .phi.W, serving as a voltage signal boosted for application to a word line, to a decoder circuit 56 through a word line driving signal line; a floating signal generating circuit 53 for receiving the word line driving signal .phi.W and the precharge start signal .phi.R before boosting, for generating a floating signal .phi.F to place a word line in an electrically floating state after a certain delay and for providing the same to the boosted signal generating circuit 55; a boost signal generating circuit 54 for receiving the floating signal .phi.F and the precharge start signal .phi.R, for generating a boost signal .phi.P for boosting a word line electrically after a certain delay and for providing the same to the boosted signal generating circuit 55; a decoder circuit 56 for performing decoding operation of signals; and a memory cell array 57 coupled to the decoder circuit 56. A control signal generating circuit 59 comprises the precharge start signal generating circuit 51, the boosting trigger signal generating circuit 52, the floating signal generating circuit 53, the boost signal generating circuit 54 and the boosted signal generating circuit 55.
The boosted signal generating circuit 55 receives the boosting trigger signal .phi.T, the precharge start signal .phi.R, the boost signal .phi.P and the floating signal .phi.F and provides a boosted word line driving signal .phi.W to a word line driving signal line coupled to an output. The word line driving signal line is connected to the word line via the decoder circuit 56 and the word line driving signal .phi.W is provided to the memory cell array 57.
As shown in M. Taniguchi et al., "Fully Boosted 64K Dynamic RAM with Automatic and Self-Refresh", IEEE Journal of Solid-State circuits, vol. SC-16, No.5, Oct. 1981, pp. 492 -498, a dynamic RAM uses a boosted word line boosted to a voltage higher than a supply voltage to ensure a wide operational margin.
FIG. 2 shows an example of a conventional boosted signal generating circuit. This conventional circuit comprises: MOS transistors 1 to 10; capacitances 11 and 12; nodes a, b and c; and a word line driving signal line W. A word line driving signal line control circuit 150 comprises the above-mentioned MOS transistors 1 to 10 and capacitance 11, and charges the signal voltage .phi.W of the word line driving signal line W up to a value approximate to a supply voltage. The capacitance 12 constitutes a capacitor circuit for boosting a charging voltage of the word line driving signal line W to a value higher than the supply voltage.
The reference character .phi.R denotes a precharge start signal; the reference character .phi.T denotes a boosting trigger signal; the reference character .phi.P denotes a boost signal; the reference character .phi.F denotes a floating signal outputted before boosting.
Referring now to a waveform diagram in FIG. 3, an operational principle of the conventional circuit is described. A dynamic RAM is brought in the so-called precharge period when the precharge signal .phi.R is at high level, the word line driving signal .phi.W is at low level, the nodes b and c are at low level and the node a is at high level.
After completion of a precharge, the transistor 3 becomes an on-state when the trigger signal .phi.T attains the high level, whereby the node c is charged. Thus, the transistor 4 becomes an on-state, a potential of the node b is kept at approximately the ground level because the transistor 6 is also in an on-state and an on resistance of the transistor 4 is set to be more than five times as large as that of the transistor 6. At the same time, the transistor 5 becomes an on-state and charges a load capacitance of the word line itself and the boost capacitance 12. Thus, the transistor 2 becomes an on-state and the transistor 6 becomes an off-state after the potential of the node a is brought to low level. At that time, the node b is charged through the transistor 4, the potential of the node c is boosted to be higher than the supply voltage V.sub.cc through capacitive coupling by means of the capacitance 11 and the word line driving signal line W is charged up to the supply voltage.
In response therefore, the signal .phi.T becomes low level and the transistors 7 and 8 become an on-state when the signal .phi.F becomes high level, with the result that potentials of the nodes b and c are brought to low level. As a result, the word line driving signal line W is brought into an electrically floating state.
Thereafter, the boost signal .phi.P becomes high level and the word line driving signal line W is boosted to be higher than the supply voltage V.sub.cc through capacitive coupling by means of the capacitance 12.
In an usual dynamic RAM, bit lines are charged up to high level and a number of bit lines are discharged at the time of sensing operation. In such case, the potential of the word line is lowered through capacitive coupling by means of the bit line and the word line as shown by a dotted line in FIG. 3 because of electrical floating of the word line as mentioned above.
Therefore, the structure of the conventional boosted signal driving circuit as mentioned above causes a decrease in voltage for writing of the memory cell, with the result that a write operation cannot be performed normally to reduce an operational margin.